Information processing systems that employ a multi-core processor system in which one system includes plural cores are recently increasing. A bus in a multi-core processor system carries various patterns of data by and from the cores. For example, data generated by a central processing unit (CPU), a direct memory access (DMA) controller, a digital signal processor (DSP), etc., flow in the bus. Access of memory by a CPU is access of which the transfer volume (i.e., volume of data transferred in one cycle) is small. Access of memory by a high-speed transferring device such as a DMA controller or a DSP is access of which the transfer volume is large.
When an information processing system is designed, design is executed such that the total number of accesses does not overflow with respect to access that is inconsistent with the transfer volume. However, when only one I/O port for items to be input and output is present or when the number of I/O ports therefor is limited, access contention may occur at the one port or each of the ports.
According to a technique to address access contention, the bus width and clock frequency are increased; the speed is further increased; and thereby, access contention is resolved (hereinafter, referred to as “conventional technique 1”). According to another technique, a memory controller controlling the input and output with respect to memory includes a queuing system that temporarily retains an access request and thereby, the effect of access contention is minimized (hereinafter, referred to as “conventional technique 2”).
According to still another technique to address access contention, a memory controller monitors cache misses and, when the number of cache misses is greater than or equal to a threshold value, reduces the transfer volume in a cycle stealing mode of the DMA (see, for example, Japanese Laid-Open Patent Publication No. 2010-15275).
However, among the conventional techniques, according to the conventional technique 1, the processing capacity is increased even at times other than when access contention occurs and therefore, a problem arises in that the power consumption increases and utilization efficiency decreases. Even when the conventional technique 2 is applied, a problem arises in that a delay in the response to an access request occurs.
In the technique according to Japanese Laid-Open Patent Publication No. 2010-15275, a problem arises in that, concerning access by a CPU, a DMA controller, a DSP, etc., it is difficult to identify which access is an access by the CPU. In the technique according to Japanese Laid-Open Patent Publication No. 2010-15275, in a case where a process having a real time restriction is under execution and the transfer volume of the DMA controller is reduced, a problem arises in that the transfer efficiency of the DMA controller drops and the real time restriction is highly likely to be violated.